1. Field of Invention
The present invention relates to a gate circuit which is operated at high speed with low consumption power by low amplitude operation signals of the semiconductor integrated circuit device, and more particularly to a semiconductor memory device or semiconductor memory circuit device characterized by high speed and high integration, and an information processing system provided with these circuits or devices.
2. Description of the Prior Art
A first prior art circuit is described in Japanese Patent Laid-Open NO. 61-293018 and Japanese Patent Laid-Open 62-186613. FIG. 18 is a sketch of this first prior art circuit.
According to this first prior art circuit, when the output signal 1809 of NMOS transistor (hereinafter referred to as "NMOS") 1806 is high, namely, (power potential)-(NMOS threshold voltage), the PMOS transistor (hereinafter referred to as "PMOS") 1810 prevents the breakthrough current of inverter 1812 from flowing and stabilizes the potential of output signal 1813.
Second prior art circuits are described in Japanese Patent Laid-open NO. 62-32722 and Japanese Patent Laid-open NO.63-5172. FIGS. 19 and 20 are sketches of these second prior art circuits.
With reference to FIG. 19 illustrating one of the second prior art circuits, PMOS Q3 is a transistor for driving transistor Q1 when signals are applied to the gate from terminal 1905, in order to drive PMOS transistor Q1 if the input signal 1901 is high. When the input signal is low, transistor Q3 turns off and operates in such a way that the high level at point A will be applied to the NMOS transistor Q2 gate, without being applied to the gate of Q1, thereby serving to increase the switching speed between Q1 and Q2.
Similarly, when input signal 1901 is high, the level at point A is low in FIG. 20. NMOS transistor Q12 is off and NMOS Q14 is on; therefore, the level at point B is also low. Accordingly, PMOS transistor Q13 is turned to drive the NMOS transistor Q11. When the level is low, the input signal 1901 at point A is high, and NMOS Q14, PMOS Q13 and NMOS Q11 are turned off. After the NMOS Q12 turns on, the output signal level turns low. At this time, all the Q11, Q13 and Q14 are turned off; therefore, almost no current runs from the 2003.
That is, transistor Q14 functions as a switching element to switch the pull-down circuit and the pull-up circuit.
A third prior art circuit widely known as the memory cell circuit used in the CMOS gate array LSI in conventional semiconductor memory device, includes the circuit used for the memory unit of a 1W-1R (one-port write-in, one-port read-out), or that used for the memory unit of a 2W-2R (two-port write-in, two-port read-out). The data memory unit of the former is composed of a CMOS inverter and a clocked inverter. The data write-in side of the data memory unit is linked to the write data line through a pair of transfer gates, and the data read-out side is linked to the read data line through the clocked inverter. Each clocked inverter comprises two PMOS transistors and two NMOS transistors, and the entire memory cell circuit is made up of six PMOS transistors and six NMOS transistors.
The data memory unit of the latter, on the other hand, comprises a pair of clocked inverters, and the data write-in side of the data memory unit is linked to the write data line through a pair of transfer gates, while the data read-out side is linked to the read data line through the read-out clocked inverter. Each clocked inverter comprises two PMOS transistors and two NMOS transistors, and the transfer gate is made up of one PMOS transistor and one NMOS transistor. The entire memory cell circuit is made up of ten PMOS transistors and ten NMOS transistors.
The first prior art circuit has associated therewith the following problem: When the potential of the clocked inverter 1809 of the NMOS transistor 1806 is high, breakthrough current flows to the inverter 1912 until feedback is applied by MOS transistor 1810.
This is because the high level of the output signal 1809 of NMOS transistor 1806 is reduced below the power potential by the threshold voltage of the NMOS transistor 1806.
Also, in the first prior art circuit the following is at issue: When the potential of the output signal 1809 of NMOS transistor 1806 is reduced from a high to a low level, the potential must be changed from the power source potential to the grounding potential, and this takes more time than the time required to change from the high level of the intermediate potential (potential reduced from power supply potential by threshold voltage of NMOS transistor 1806) to the grounding potential.
The above-recognized problem is caused by the PMOS transistor 1810, provided to avoid breakthrough current of the inverter 1812.
Unlike the circuit according to the present invention, the second prior art circuit provides a circuit where a high voltage circuit is driven by a low voltage CMOS circuit to produce high voltage signals.
This requires two or more different power supply voltages to be provided, resulting in a complicated structure of the power supply system.
Furthermore, according to the second prior art circuit, signals at point A are driven by the complementary circuit comprising transistors Q4 and Q5, and the potential at point A provides the same amplitude as that of the power supply voltage. Accordingly, the complementary circuit comprising transistors Q4 and Q5 has little effect in reducing power consumption since it reduces the charging and discharging current at point A. Furthermore, operation amplitude at point A is the same as that of power supply voltage, so it is less effective in increasing speed by reducing signal amplitude. Moreover, when the level o input signal 1901 is high, direct current will flow through R1, Q3 and Q4, and R1, Q14 and Q4, resulting in increased power consumption.
In the third prior art circuit, each six or ten PMOS transistors and six NMOS transistors are used to configure the memory cell circuit. When the basic cell is made up of two pairs of two-series PMOS transistors and two-series NMOS transistors (eight transistor in total), for example, the former requires a minimum of 1.5 BCs (basic cells), while the latter requires a minimum of 2.5 BCs (basic cells), resulting in increased area of the memory cell circuit. The read data line is linked to a read-out clocked inverter for each memory cell, and the read data line must be provided with an additional drain capacity for two transistors of the clocked inverter; PMOS transistor and NMOS transistor, causing the read data line load capacity and the memory access time to be increased.
One object of the present invention is to provide a semiconductor integrated circuit which operates at low power consumption from a single power supply without any breakthrough current, despite reception of input signals of low amplitude operation.
Another object of the present invention is to provide a semiconductor integrated circuit device where the input signal transition time is shortened by reducing the amplitude of input signals, and power consumption in a driver circuit to drive said input signals is reduced.
Still another object of the present invention is to provide a semiconductor memory device characterized by high speed and low power consumption, plus high memory density of the master slide type LSI such as gate array and embedded array.
A further object of the present invention is to provide a semiconductor integrated circuit device and semiconductor memory device, which allow reduction of the capacity to be added to the data line.